Modern signal processing systems often use non-volatile memory to store data; such data comprising data to be processed, as well as instruction code and the like. One such non-volatile computer storage technology is Flash memory, which is a specific type of EEPROM (electrically erasable programmable read-only memory), that is capable of being erased and programmed in large blocks. Flash memory advantageously costs far less than byte-programmable EPROM (erasable programmable read-only memory), and as such has become a dominant technology wherever a significant amount of non-volatile, solid state storage is required.
However, Flash memory has a relatively slow access time compared with the speed of, say, a processing core or other communication bus master device accessing the memory. For example, for a processing core comprising an operating frequency of, say, 200 MHz, it would take approximately eight cycles of the processing core for a read access to be made directly from Flash memory with a read-access time of approximately 40 nsec. Such a delay in a processing core being able to access data can have a serious impact on overall system performance.
In order to improve the overall data throughput from Flash memory and the like, it is known to use prefetch mechanisms that make speculative data fetches from the Flash memory, and store the prefetched data in a small, relatively fast memory array buffer. In this manner, the prefetched data is ready to be accessed before the processing core, or other bus master device, has requested the data. Such speculative prefetching of data works well for linear code (e.g. code that executes from sequential addresses with no change of flow), since future read access requests are highly predictable. However, for code that has frequent changes of flow, such speculative prefetching can have a detrimental effect on system performance when unnecessary speculative prefetches occur. For example, data fetching from Flash memory is typically non-abortable due to typical architectures used for Flash memory. As a result, if, during a speculative prefetch, a data access is received from, say, a processing core for data not already prefetched (e.g. due to a flow change), an access of the Flash memory to retrieve the requested data must wait until the pending speculative prefetch access has completed. As such, an already slow access from the Flash memory is delayed even further.
A further problem with the use of prefetching mechanisms is that speculative prefetches of data that is not immediately required consume valuable buffer space, and unnecessarily remove previously fetched data from the buffer. As a result, the likelihood of a further access being necessary to retrieve the removed data is increased, thereby potentially delaying access to such data.
As signal processing systems are increasingly moving towards multiple-core architectures, where multiple bus-master devices require access to the same Flash arrays, the demands on prefetch mechanisms (and the associated buffer space) are increasing, and, thus, the instances of bus contentions are likely to increase. In such instances, it is especially important to avoid unnecessary speculative prefetches of data.
Furthermore, with current advances to higher operating frequencies, and with a current move towards relatively longer latency (lower cost) Flash memory modules, the efficiency of caches and prefetching mechanisms is becoming an increasingly significant factor in signal processing systems.